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1998 data sheet the mark shows major revised points. pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) mos integrated circuit description the pd703003a, 703004a, 703025a, 703003a(a), and 703025a(a) are members of the v850 series tm of 32- bit single-chip microcontrollers designed for real-time control operations. these microcontrollers provide on-chip features including a 32-bit cpu core, rom, ram, an interrupt controller, a real-time pulse unit, a serial interface, an a/d converter, a d/a converter, and pwm. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. v853 hardware user? manual: u10913e v850 series architecture user? manual: u10243e features number of instructions: 74 advanced internal interrupt controller minimum instruction execution time: real-time pulse unit suitable for control operations 30 ns (@ 33 mhz operation) powerful serial interface general-purpose registers: 32 bits 32 registers (with on-chip dedicated baud rate generator) instruction set optimized for control applications on-chip clock generator internal memory 10-bit resolution a/d converter: 8 channels rom: 256 kb ( pd703025a, 703025a(a)) 8-bit resolution d/a converter: 2 channels 128 kb ( pd703003a, 703003a(a)) 8-/9-/10-/12-bit resolution pwm: 2 channels 96 kb ( pd703004a) power saving functions ram: 8 kb ( pd703025a, 703025a(a)) 4 kb ( pd703003a, 703004a, 703003a(a)) ordering information part number package quality grade pd703003agc-33- -8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd703004agc-33- -8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd703025agc-33- -8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd703003agc(a)-33- -8eu 100-pin plastic lqfp (fine pitch) (14 14) special pd703025agc(a)-33- -8eu 100-pin plastic lqfp (fine pitch) (14 14) special remark indicates rom code suffix. the pd703003a, 703025a and pd703003a(a), 703025a(a) differ in the quality grade only. v853 tm 32-bit single-chip microcontrollers document no. u13188ej6v0ds00 (6th edition) date published january 2002 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 2 data sheet u13188ej6v0ds applications pd703003a, 703004a, 703025a: camcorders, vcrs, ppcs, lbps, printers, motor controllers, nc machine tools, mobile telephones, etc. pd703003a(a), 703025a(a): medical equipment, automotive appliances, etc. pin configuration 100-pin plastic lqfp (fine pitch) (14 14) pd703003agc-33- -8eu pd703003agc(a)-33- -8eu pd703004agc-33- -8eu pd703025agc(a)-33- -8eu pd703025agc-33- -8eu caution connect the ic (internally connected) pin directly to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ano0 ano1 av ref2 av ref3 p07/intp113/adtrg p06/intp112 p05/intp111 p04/intp110 p03/ti11 p02/tclr11 p01/to111 p00/to110 p117/intp143 p116/intp142 p115/intp141 p114/intp140 p113/ti14 p112/tclr14 p111/to141 p31/to131 p32/tclr13 p33/ti13 p34/intp130 p35/intp131/so3 p36/intp132/si3 p37/intp133/sck3 p63/a19 p62/a18 p61/a17 p60/a16 v ss v dd p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 v ss v dd p41/ad1 p40/ad0 p90/lben p91/uben p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq wait ic mode reset cv dd /cksel x2 x1 cv ss clkout v ss v dd p110/to140 p30/to130 p27/sck1 p26/rxd1/si1 p25/txd1/so1 p24/sck0 p23/rxd0/si0 p22/txd0/so0 p21/pwm1 p20/pwm0 nmi v dd v ss p17/intp123/sck2 p16/intp122/si2 p15/intp121/so2 p14/intp120 p13/ti12 p12/tclr12 p11/to121 p10/to120 av dd av ss av ref1 p77/ani7 p76/ani6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
3 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds pin names a16 to a19: address bus p30 to p37: port 3 ad0 to ad15: address/data bus p40 to p47: port 4 adtrg: a/d trigger input p50 to p57: port 5 ani0 to ani7: analog input p60 to p63: port 6 ano0, ano1: analog output p70 to p77: port 7 astb: address strobe p90 to p96: port 9 av dd : analog power supply p110 to p117: port 11 av ref1 to av ref3 : analog reference voltage pwm0, pwm1: pulse width modulation av ss : analog ground reset: reset cv dd : power supply for clock generator r/w: read/write status cv ss : ground for clock generator rxd0, rxd1: receive data cksel: clock select sck0 to sck3: serial clock clkout: clock output si0 to si3: serial input dstb: data strobe so0 to so3: serial output hldak: hold acknowledge to110, to111, hldrq: hold request to120, to121, ic: internally connected to130, to131, intp110 to intp113, to140, to141: timer output intp120 to intp123, tclr11 to tclr14: timer clear intp130 to intp133, ti11 to ti14: timer input intp140 to intp143: interrupt request from peripherals txd0, txd1: transmit data lben: lower byte enable uben: upper byte enable mode: mode wait: wait nmi: non-maskable interrupt request x1, x2: crystal p00 to p07: port 0 v dd : power supply p10 to p17: port 1 v ss : ground p20 to p27: port 2
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 4 data sheet u13188ej6v0ds internal block diagram notes 1. pd703003a, 703003a(a): 128 kb pd703004a: 96 kb pd703025a, 703025a(a): 256 kb 2. pd703003a, 703004a, 703003a (a): 4 kb pd703025a, 703025a(a): 8 kb nmi to110, to111 to120, to121 to130, to131 to140, to141 intp110 to intp113 intp120 to intp123 intp130 to intp133 intp140 to intp143 tclr11 to tclr14 ti11 to ti14 intc rpu sio mask rom ram note 2 note 1 cpu pc 32-bit barrel shifter system registers general- purpose registers 32 bits 32 alu multiplier 16 16 32 port p110 to p117 p90 to p96 p70 to p77 p60 to p63 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p17 p00 to p07 cg bcu instruction queue astb dstb r/w uben lben wait a16 to a19 ad0 to ad15 hldrq hldak clkout x1 x2 mode reset uart0/csi0 brg0 uart1/csi1 brg1 csi2 brg2 csi3 pwm so0/txd0 si0/rxd0 sck0 so1/txd1 si1/rxd1 sck1 so2 si2 sck2 so3 si3 sck3 pwm0, pwm1 a/d converter ani0 to ani7 av ref1 av ss av dd adtrg d/a converter ano0, ano1 av ref2 , av ref3 v dd v ss cv dd cv ss cksel
5 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds contents 1. differences between products ........................................................................................ 6 2. pin functions ................................................................................................................ .............. 7 2.1 port pins ................................................................................................................... ............................. 7 2.2 non-port pins ............................................................................................................... ......................... 9 2.3 pin i/o circuits and recommended connection of unused pins .................................................... 11 3. electrical specifications .................................................................................................... 14 4. package drawing .............................................................................................................. ....... 35 5. recommended soldering conditions ............................................................................... 36 appendix notes on target system design ........................................................................... 37
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 6 data sheet u13188ej6v0ds 1. differences between products item pd703003a pd703004a pd703025a pd703003a(a) pd703025a(a) pd70f3003a pd70f3025a pd70f3003a(a) internal rom mask rom flash memory 128 kb 96 kb 256 kb 128 kb 256 kb 128 kb 256 kb 128 kb internal ram 4 kb 8 kb 4 kb 8 kb 4 kb 8 kb 4 kb flash memory none provided programming mode v pp pin none provided quality grade standard special standard special electrical specifications current consumption, etc. differs. (refer to each product data sheets.) others noise immunity and noise radiation differ because circuit scale and mask layout differ. caution there are differences in noise immunity and noise radiation between the flash memory version and mask rom version. when pre-producing an application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask rom version.
7 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds 2. pin functions 2.1 port pins (1/2) pin name i/o function alternate function p00 i/o port 0 to110 p01 8-bit i/o port to111 p02 input/output can be specified in 1-bit units. tclr11 p03 ti11 p04 intp110 p05 intp111 p06 intp112 p07 intp113/adtrg p10 i/o port 1 to120 p11 8-bit i/o port to121 p12 input/output can be specified in 1-bit units. tclr12 p13 ti12 p14 intp120 p15 intp121/so2 p16 intp122/si2 p17 intp123/sck2 p20 i/o port 2 pwm0 p21 8-bit i/o port pwm1 p22 input/output can be specified in 1-bit units. txd0/so0 p23 rxd0/si0 p24 sck0 p25 txd1/so1 p26 rxd1/si1 p27 sck1 p30 i/o port 3 to130 p31 8-bit i/o port to131 p32 input/output can be specified in 1-bit units. tclr13 p33 ti13 p34 intp130 p35 intp131/so3 p36 intp132/si3 p37 intp133/sck3 p40 to p47 i/o port 4 ad0 to ad7 8-bit i/o port input/output can be specified in 1-bit units. p50 to p57 i/o port 5 ad8 to ad15 8-bit i/o port input/output can be specified in 1-bit units.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 8 data sheet u13188ej6v0ds (2/2) pin name i/o function alternate function p60 to p63 i/o port 6 a16 to a19 4-bit i/o port input/output can be specified in 1-bit units. p70 to p77 input port 7 ani0 to ani7 8-bit input port p90 i/o port 9 lben p91 7-bit i/o port uben p92 input/output can be specified in 1-bit units. r/w p93 dstb p94 astb p95 hldak p96 hldrq p110 i/o port 11 to140 p111 8-bit i/o port to141 p112 input/output can be specified in 1-bit units. tclr14 p113 ti14 p114 intp140 p115 intp141 p116 intp142 p117 intp143
9 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds 2.2 non-port pins (1/2) pin name i/o function alternate function to110 output pulse signal output from timers 11 to 14 p00 to111 p01 to120 p10 to121 p11 to130 p30 to131 p31 to140 p110 to141 p111 tclr11 input external clear signal input for timers 11 to 14 p02 tclr12 p12 tclr13 p32 tclr14 p112 ti11 input external count clock input for timers 11 to 14 p03 ti12 p13 ti13 p33 ti14 p113 intp110 input external maskable interrupt request input, also used as external capture p04 intp111 trigger input for timer 11 p05 intp112 p06 intp113 p07/adtrg intp120 input external maskable interrupt request input, also used as external capture p14 intp121 trigger input for timer 12 p15/so2 intp122 p16/si2 intp123 p17/sck2 intp130 input external maskable interrupt request input, also used as external capture p34 intp131 trigger input for timer 13 p35/so3 intp132 p36/si3 intp133 p37/sck3 intp140 input external maskable interrupt request input, also used as external capture p114 intp141 trigger input for timer 14 p115 intp142 p116 intp143 p117 so0 output serial transmit data output for csi0 to csi3 (3-wire) p22/txd0 so1 p25/txd1 so2 p15/intp121 so3 p35/intp131 si0 input serial receive data input for csi0 to csi3 (3-wire) p23/rxd0 si1 p26/rxd1 si2 p16/intp122 si3 p36/intp132
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 10 data sheet u13188ej6v0ds (2/2) pin name i/o function alternate function sck0 i/o serial clock i/o for csi0 to csi3 (3-wire) p24 sck1 p27 sck2 p17/intp123 sck3 p37/intp133 txd0 output serial transmit data output for uart0 and uart1 p22/so0 txd1 p25/so1 rxd0 input serial receive data input for uart0 and uart1 p23/si0 rxd1 p26/si1 pwm0 output pwm pulse signal output p20 pwm1 p21 ad0 to ad7 i/o 16-bit multiplexed address/data bus for external memory expansion p40 to p47 ad8 to ad15 p50 to p57 a16 to a19 output higher address bus used for external memory expansion p60 to p63 lben output external data bus? lower byte enable signal output p90 uben external data bus? higher byte enable signal output p91 r/w output external read/write status output p92 dstb external data strobe signal output p93 astb external address strobe signal output p94 hldak output bus hold acknowledge output p95 hldrq input bus hold request input p96 ani0 to ani7 input analog input to a/d converter p70 to p77 ano0, ano1 output analog output from d/a converter nmi input non-maskable interrupt request input clkout output system clock output cksel input input for specifying clock generator? operation mode cv dd wait input control signal input for inserting wait in bus cycle mode input operation mode specification reset input system reset input x1 input resonator connection for system clock. input is via x1 when using an x2 external clock. adtrg input a/d converter external trigger input p07/intp113 av ref1 input reference voltage input for a/d converter av ref2 input reference voltage input for d/a converter av ref3 av dd positive power supply for a/d converter av ss ground potential for a/d converter cv dd positive power supply for on-chip clock generator cksel cv ss ground potential for on-chip clock generator v dd positive power supply v ss ground potential ic internally connected pin (connect directly to v ss )
11 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds 2.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 2-1. figure 2- 1 illustrates the various circuit types using partially abridged diagrams. it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via a resistor. table 2-1. types of pin i/o circuits and recommended connection of unused pins (1/2) pin name i/o circuit type recommended connection of unused pins p00/to110, p01/to111 5 input: independently connect to v dd or v ss via a resistor. p02/tclr11, p03/ti11, 8 output: leave open. p04/intp110 to p07/intp113/adtrg p10/to120, p11/to121 5 p12/tclr12, p13/ti12 8 p14/intp120 p15/intp121/so2 p16/intp122/si2 p17/intp123/sck2 p20/pwm0, p21/pwm1 5 p22/txd0/so0 p23/rxd0/si0, p24/sck0 8 p25/txd1/so1 5 p26/rxd1/si1, p27/sck1 8 p30/to130, p31/to131 5 p32/tclr13, p33/ti13 8 p34/intp130 p35/intp131/so3 10-a p36/intp132/si3 p37/intp133/sck3 p40/ad0 to p47/ad7 5 p50/ad8 to p57/ad15 p60/a16 to p63/a19 p70/ani0 to p77/ani7 9 connect directly to v ss . p90/lben 5 input: independently connect to v dd or v ss via a resistor. p91/uben output: leave open. p92/r/w p93/dstb p94/astb p95/hldak p96/hldrq p110/to140, p111/to141 p112/tclr14, p113/ti14 8 p114/intp140 to p117/intp143 ano0, ano1 12 leave open. nmi 2 connect directly to v ss .
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 12 data sheet u13188ej6v0ds table 2-1. types of pin i/o circuits and recommended connection of unused pins (2/2) pin name i/o circuit type recommended connection of unused pins clkout 3 leave open. wait 1 connect directly to v dd . mode 2 reset cv dd /cksel av ref1 to av ref3 , av ss connect directly to v ss . av dd connect directly to v dd . ic connect directly to v ss .
13 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds figure 2-1. pin i/o circuits type 1 type 2 type 8 type 3 p-ch n-ch in v dd in schmitt-triggered input with hysteresis characteristics p-ch n-ch v dd out p-ch n-ch v dd in/out data output disable type 5 p-ch n-ch v dd in/out data output disable input enable in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable open drain type10-a out p-ch n-ch analog output voltage type 12
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 14 data sheet u13188ej6v0ds 3. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd v dd pin ?.5 to +7.0 v cv dd cv dd pin ?.5 to v dd + 0.3 note 1 v cv ss cv ss pin ?.5 to +0.5 v av dd av dd pin ?.5 to v dd + 0.3 note 1 v av ss av ss pin ?.5 to +0.5 v input voltage v i1 note 2 , v dd = 5.0 v 10% ?.5 to v dd + 0.3 note 1 v clock input voltage v k x1 pin, v dd = 5.0 v 10% ?.5 to v dd + 1.0 note 1 v output current, low i ol per pin 4.0 ma total for all pins 100 ma output current, high i oh per pin ?.0 ma total for all pins ?00 ma output voltage v o v dd = 5.0 v 10% ?.5 to v dd + 0.3 note 1 v analog input voltage v ian p70/ani0 to p77/ani7 av dd > v dd ?.5 to v dd + 0.3 note 1 v v dd av dd ?.5 to av dd + 0.3 note 1 v analog reference input voltage av ref av ref1 to av ref3 av dd > v dd ?.5 to v dd + 0.3 note 1 v v dd av dd ?.5 to av dd + 0.3 note 1 v operating ambient temperature t a ?0 to +85 c storage temperature t stg ?5 to +150 c notes 1. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 2. x1, p70 to p77, av ref1 to av ref3 , and their alternate-function pins are excluded. cautions 1. avoid direct connections among the ic device output (or i/o) pins and between v dd or v cc and gnd. however, direct connections among open-drain and open-collector pins are possible, as are direct connections to external circuits that have timing designed to prevent output conflict with pins that become high-impedance. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol condition min. typ. max. unit input capacitance c i f c = 1 mhz 15 pf i/o capacitance c io unmeasured pins returned to 0 v. 15 pf output capacitance c o 15 pf
15 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds operating conditions operation mode internal system clock frequency ( ) operating ambient power supply temperature (t a ) voltage (v dd ) direct mode, pll mode 2 to 33 mhz note 1 40 to +85 c 5.0 v 10% 5 to 33 mhz note 2 40 to +85 c 5.0 v 10% notes 1. when not using a/d converter 2. when using a/d converter recommended oscillator caution for the resonator selection and oscillator constant of the pd703003a(a) and 703025a(a), customers are requested to apply to the resonator manufacturer for evaluation. (1) ceramic resonator connection (t a = ?0 to +85 c) (a) pd703003a, 703004a x1 x2 c1 c2 rd manufacturer part number oscillation recommended oscillation oscillation frequency circuit constant voltage range stabilization time f xx (mhz) c1 (pf) c2 (pf) rd ( ? ) min. (v) max. (v) (max.) t ost (ms) kyocera pbrc5.00b 5.0 on-chip on-chip 680 4.5 5.5 0.14 corporation pbrc6.60b 6.6 on-chip on-chip 4.5 5.5 0.08 tdk ccr5.0mc3 5.0 on-chip on-chip 4.5 5.5 0.19 fcr5.0mc5 5.0 on-chip on-chip 4.5 5.5 0.16 ccr6.6mc3 6.6 on-chip on-chip 4.5 5.5 0.17 murata mfg. csa5.00mg040 5.0 100 100 4.5 5.5 0.32 co., ltd cst5.00mgw040 5.0 on-chip on-chip 4.5 5.5 0.32 csa6.60mtz040 6.6 100 100 4.5 5.5 0.72 cst6.60mtw040 6.6 on-chip on-chip 4.5 5.5 0.72 cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703003a or 703004a and the resonator.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 16 data sheet u13188ej6v0ds kyocera pbrc4.00hr 4.0 on-chip on-chip 4.5 5.5 0.08 corporation pbrc5.00hr 5.0 on-chip on-chip 4.5 5.5 0.06 pbrc6.00hr 6.0 on-chip on-chip 4.5 5.5 0.08 pbrc6.60hr 6.6 on-chip on-chip 4.5 5.5 0.08 tdk ccr4.0mc3 4.0 on-chip on-chip 4.5 5.5 0.22 ccr5.0mc3 5.0 on-chip on-chip 4.5 5.5 0.28 murata mfg. csa4.00mg040 4.0 100 100 4.5 5.5 0.40 co., ltd cst4.00mgw040 4.0 on-chip on-chip 4.5 5.5 0.40 csts0400mg06 4.0 on-chip on-chip 4.5 5.5 0.16 csa6.60mtz040 6.6 100 100 4.5 5.5 0.50 cst6.60mtw040 6.6 on-chip on-chip 4.5 5.5 0.50 csts0660mg06 6.6 on-chip on-chip 4.5 5.5 0.20 (b) pd703025a x1 x2 c1 c2 rd manufacturer part number oscillation recommended oscillation oscillation frequency circuit constant voltage range stabilization time f xx (mhz) c1 (pf) c2 (pf) rd ( ? ) min. (v) max. (v) (max.) t ost (ms) cautions 1. connect the oscillator as closely to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. thoroughly evaluate the matching between the pd703025a and the resonator. (2) external clock input x1 high-speed cmos inverter external clock x2 open cautions 1. put the high-speed cmos inverter as close to the x1 pins as possible. 2. sufficiently evaluate the matching between the pd703003a, 703004a, 703025a, 703003a(a), or 703025a(a) and the high-speed cmos inverter.
17 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds dc characteristics (t a = ?0 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih except for x1 and pins listed in note1 2.2 v dd + 0.3 v note 1 0.8v dd v dd + 0.3 v input voltage, low v il except for x1 and pins listed in note1 0.5 +0.8 v note 1 0.5 0.2v dd v clock input voltage, high v xh x1 0.8v dd v dd + 0.5 v clock input voltage, low v xl x1 0.5 +0.6 v schmitt-triggered input v t + note 1 , rising edge 3.0 v threshold voltage v t note 1 , falling edge 2.0 v schmitt-triggered input hysteresis width v t + v t note 1 0.5 v output voltage, high v oh i oh = 2.5 ma 0.7v dd v i oh = 100 av dd 0.4 v output voltage, low v ol i ol = 2.5 ma 0.45 v input leakage current, high i lih v i = v dd 10 a input leakage current, low i lil v i = 0 v 10 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v 10 a software pull-up resistor r p35 to p37 and their 15 40 90 k ? alternate-function pins power pd703003a, when i dd1 direct mode 1.9 + 5 2.1 + 17 ma supply 703004a, operating pll mode 2.0 + 7 2.2 + 20 ma current 703003a(a) in i dd2 direct mode 1.2 + 5 1.3 + 13 ma halt mode pll mode 1.3 + 7 1.4 + 15 ma in i dd3 direct mode 8 + 300 10 + 500 a idle mode pll mode 0.1 + 2 0.2 + 3 ma in i dd4 note 2 250 a stop mode note 3 2 200 a pd703025a, when i dd1 direct mode 2.5 + 2 2.8 + 16.5 ma 703025a(a) operating pll mode 2.6 + 4 2.9 +19.5 ma in i dd2 direct mode 1.3 + 5 1.4 + 13 ma halt mode pll mode 1.3 + 10 1.4 + 18 ma in i dd3 direct mode 8 + 300 10 + 500 a idle mode pll mode 0.1 + 2 0.2 + 3 ma in i dd4 note 2 250 a stop mode note 3 2 200 a notes 1. p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, and their alternate-function pins. 2. 40 c t a +50 c 3. 50 c < t a 85 c remarks 1. typ. values are reference values for when t a = 25 c (except for the conditions in note 3 ) and v dd = 5.0 v. the power supply current does not include av ref1 to av ref3 or the current that flows through software pull-up resistors. 2. = internal system clock frequency
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 18 data sheet u13188ej6v0ds data retention characteristics (t a = ?0 to +85 c, v dd = v dddr ) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.5 5.5 v data retention current i dddr note 1 0.4v dddr 50 a note 2 0.4v dddr 200 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage hold time t hvd 0ms (vs. stop mode setting) stop mode release signal input time t drel note 3 0ns data retention high-level input voltage v ihdr note 3 0.9v dddr v dddr v data retention low-level input voltage v ildr 0 0.1v dddr v notes 1. 40 c t a +50 c 2. 50 c 19 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds ac characteristics (t a = ?0 to +85 c, v dd = 5.0 v 10%, v ss = 0 v) ac test input test points (a) p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, x1, and their alternate-function pins (b) pins other than those listed in (a) above ac test output test points load condition caution in cases where the load capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other element to reduce the device? load capacitance to below 50 pf. c l = 50 pf dut (device under testing) test points 0.8v dd 0.2v dd 0.8v dd 0.2v dd v dd 0 v test points 2.2 v 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v test points 2.2 v 0.8 v 2.2 v 0.8 v
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 20 data sheet u13188ej6v0ds (1) clock timing parameter symbol conditions min. max. unit x1 input cycle <1> t cyx direct mode 15 note 1 ns pll mode (pll locked) 151 note 2 note 3 ns x1 input high-level width <2> t wxh direct mode 6 ns pll mode 60 ns x1 input low-level width <3> t wxl direct mode 6 ns pll mode 60 ns x1 input rise time <4> t xr direct mode 7 ns pll mode 10 ns x1 input fall time <5> t xf direct mode 7 ns pll mode 10 ns cpu operating frequency note 4 33 mhz clkout output cycle <6> t cyk 30 note 5 ns clkout input high-level width <7> t wkh 0.5t 5ns clkout input low-level width <8> t wkl 0.5t 5ns clkout input rise time <9> t kr 5ns clkout input fall time <10> t kf 5ns delay time from x1 to clkout <11> t dxk direct mode 3 17 ns notes 1. when using a/d converter: 100 ns when not using a/d converter: 250 ns 2. when using a/d converter: the value when = 5 f xx and = f xx are set. setting = 1/2 f xx is prohibited. when not using a/d converter: the value when = 5 f xx , = f xx , and = 1/2 f xx are set. 3. when using a/d converter: 250 ns (when = 5 f xx is set) and 200 ns (when = f xx is set). setting = 1/2 f xx is prohibited. when not using a/d converter: 250 ns (when = 5 f xx , = f xx , and = 1/2 f xx are set). 4. when using a/d converter: 5 mhz when not using a/d converter: 2 mhz 5. when using a/d converter: 200 ns when not using a/d converter: 500 ns remark t = t cyk x1 (input) clkout (output) <1> <2> <4> <5> <6> <7> <11> <11> <8> <9> <10> <3>
21 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds (b) pins other than those listed in (a) above parameter symbol conditions min. max. unit input rise time <14> t ir1 10 ns input fall time <15> t if1 10 ns (2) input waveform (a) p02 to p07, p12 to p17, p23, p24, p26, p27, p32 to p37, p112 to p117, reset, nmi, mode, and their alternate-function pins parameter symbol conditions min. max. unit input rise time <12> t ir2 20 ns input fall time <13> t if2 20 ns (3) output waveform (other than clkout) parameter symbol conditions min. max. unit output rise time <16> t or 10 ns output fall time <17> t of 10 ns 2.2 v <15> <14> 0.8 v 2.2 v 0.8 v 2.4 v 0.4 v input signal 0.8v dd 0.2v dd 0.8v dd 0.2v dd v dd 0 v <13> <12> input signal 0.8 v <16> <17> 2.2 v 2.2 v 0.8 v output signal
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 22 data sheet u13188ej6v0ds (4) reset timing parameter symbol conditions min. max. unit reset high-level width <18> t wrsh 500 ns reset low-level width <19> t wrsl when power supply is on 500 + t ost ns and stop mode has been released other than when power 500 ns supply is on and stop mode has been released remark t ost : oscillation stabilization time reset (input) <18> <19>
23 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds delay time from clkout to astb <22> t dkst 3 15 ns delay time from clkout to dstb <23> t dkd 3 15 ns data input setup time (to clkout ) <24> t sidk 5 ns data input hold time (from clkout ) <25> t hkid 5 ns wait setup time (to clkout ) <26> t swtk 5 ns wait hold time (from clkout ) <27> t hkwt 5 ns address hold time (from clkout ) <28> t hka 0 ns address setup time (to astb ) <29> t sast 40 c t a +70 c 0.5t 10 ns 70 c < t a 85 c 0.5t 12 ns address hold time (from astb ) <30> t hsta 0.5t 10 ns delay time from dstb to address float <31> t fda 0 ns data input setup time (to address) <32> t said 40 c t a +70 c (2 + n)t 22 ns 70 c < t a 85 c (2 + n)t 25 ns data input setup time (to dstb ) <33> t sdid 40 c t a +70 c (1 + n)t 20 ns 70 c < t a 85 c (1 + n)t 24 ns delay time from astb to dstb <34> t dstd 0.5t 10 ns data input hold time (from dstb ) <35> t hdid 0 ns delay time from dstb to address output <36> t dda (1 + i)t ns delay time from dstb to astb <37> t ddsth 0.5t 10 ns delay time from dstb to astb <38> t ddstl (1.5 + i)t 10 ns dstb low-level width <39> t wdl 40 c t a +70 c (1 + n)t 10 ns 70 c < t a 85 c (1 + n)t 13 ns astb high-level width <40> t wsth t 10 ns wait setup time (to address) <41> t sawt1 n 1, 40 c t a +70 c 1.5t 20 ns n 1, 70 c < t a 85 c 1.5t 24 ns <42> t sawt2 n 1, 40 c t a +70 c (1.5 + n)t 20 ns n 1, 70 c < t a 85 c (1.5 + n)t 24 ns wait hold time (from address) <43> t hawt1 n 1 (0.5 + n)t ns <44> t hawt2 n 1 (1.5 + n)t ns wait setup time (to astb ) <45> t sstwt1 n 1, 40 c t a +70 c t 18 ns n 1, 70 c < t a 85 c t 20 ns <46> t sstwt2 n 1 (1 + n)t 15 ns wait hold time (from astb ) <47> t hstwt1 n 1 nt ns <48> t hstwt2 n 1 (1 + n)t ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. maintain at least one of the two data input hold times, either t hkid (<25>) or t hdid (<35>). (5) read timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <20> t dka 3 20 ns delay time from clkout to r/w, uben, lben <78> t dka2 2 +13 ns delay time from clkout to address float <21> t fka 3 15 ns
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 24 data sheet u13188ej6v0ds t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0 to ad15 (i/o) astb (output) dstb (output) wait (input) <32> <20> r/w (output) uben (output) lben (output) <78> <28> <25> <24> <21> a0 to a15 (output) d0 to d15 (input) <22> <29> <22> <35> <37> <36> <23> <31> <34> <40> <33> <23> <39> <38> <26> <27> <26> <47> <46> <48> <27> <45> <41> <44> <43> <42> <30> (5) read timing (2/2): 1 wait remark broken lines indicate high impedance.
25 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds (6) write timing (1/2) parameter symbol conditions min. max. unit delay time from clkout to address <20> t dka 3 20 ns delay time from clkout to r/w, uben, lben <78> t dka2 2 +13 ns delay time from clkout to astb <22> t dkst 3 15 ns delay time from clkout to dstb <23> t dkd 3 15 ns wait setup time (to clkout ) <26> t swtk 5 ns wait hold time (from clkout ) <27> t hkwt 5 ns address hold time (from clkout ) <28> t hka 0 ns address setup time (to astb ) <29> t sast 40 c t a +70 c 0.5t 10 ns 70 c < t a 85 c 0.5t 12 ns address hold time (from astb ) <30> t hsta 0.5t 10 ns delay time from astb to dstb <34> t dstd 0.5t 10 ns delay time from dstb to astb <37> t ddsth 0.5t 10 ns dstb low-level width <39> t wdl 40 c t a +70 c (1 + n)t 10 ns 70 c < t a 85 c (1 + n)t 13 ns astb high-level width <40> t wsth t 10 ns wait setup time (to address) <41> t sawt1 n 1, 40 c t a +70 c 1.5t 20 ns n 1, 70 c < t a 85 c 1.5t 24 ns <42> t sawt2 n 1, 40 c t a +70 c (1.5 + n)t 20 ns n 1, 70 c < t a 85 c (1.5 + n)t 24 ns wait hold time (from address) <43> t hawt1 n 1 (0.5 + n)t ns <44> t hawt2 n 1 (1.5 + n)t ns wait setup time (to astb ) <45> t sstwt1 n 1, 40 c t a +70 c t 18 ns n 1, 70 c < t a 85 c t 20 ns <46> t sstwt2 n 1 (1 + n)t 15 ns wait hold time (from astb ) <47> t hstwt1 n 1 nt ns <48> t hstwt2 n 1 (1 + n)t ns address hold time (from clkout ) <49> t dkod 40 c t a +70 c 20 ns 70 c < t a 85 c 23 ns delay time from dstb to data output <50> t ddod 10 ns data output hold time (from clkout ) <51> t hkod 0 ns data output setup time (to dstb ) <52> t sodd (1 + n)t 15 ns data output hold time (from dstb ) <53> t hdod t 10 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 26 data sheet u13188ej6v0ds remark broken lines indicate high impedance. (6) write timing (2/2): 1 wait t1 t2 tw t3 clkout (output) a16 to a19 (output) ad0 to ad15 (i/o) astb (output) dstb (output) wait (input) <20> <78> <28> <49> a0 to a15 (output) d0 to d15 (output) <22> <29> <30> <22> <37> <53> <23> <50> <23> <40> <52> <34> <39> <26> <27> <26> <47> <46> <48> <27> <45> <41> <44> <43> <42> <51> r/w (output) uben (output) lben (output)
27 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds (7) bus hold timing (1/2) parameter symbol conditions min. max. units hldrq setup time (to clkout ) <54> t shqk 5 ns hldrq hold time (from clkout ) <55> t hkhq 5 ns hldak delay time from clkout <56> t dkha 20 ns hldrq high-level width <57> t whqh t + 10 ns hldak low-level width <58> t whal 40 c t a +70 c t 10 ns 70 c < t a 85 c t 12 ns delay time from clkout to bus float <59> t dkf 20 ns delay time from hldak to bus output <60> t dhac 3ns delay time from hldrq to hldak <61> t dhqha1 (2n + 7.5)t + 20 ns delay time from hldrq to hldak <62> t dhqha2 0.5t 1.5t + 20 ns remarks 1. t = t cyk 2. n indicates the number of wait clocks that are inserted during a bus cycle. the sampling timing may vary when using the programmable wait insertion function.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 28 data sheet u13188ej6v0ds (7) bus hold timing (2/2) note uben (output), lben (output) remark broken lines indicate high impedance. th th th ti th clkout (output) a16 to a19 (output), note hldak (output) dstb (output) r/w (output) hldrq (input) astb (output) ad0 to ad15 (i/o) d0 to d15 (input or output) <55> <61> <62> <57> <54> <54> <56> <58> <56> <60> <59>
29 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds (8) interrupt timing parameter symbol conditions min. max. unit nmi high-level width <63> t wnih 500 ns nmi low-level width <64> t wnil 500 ns intpn high-level width <65> t with n = 110 to 113, 120 to 123, 3t + 10 ns 130 to 133, 140 to 143 intpn low-level width <66> t witl n = 110 to 113, 120 to 123, 3t + 10 ns 130 to 133, 140 to 143 remark t = t cyk nmi (input) <63> <64> intpn (input) <65> <66> remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 30 data sheet u13188ej6v0ds (9) csi timing (1/2) (a) master mode (i) timing of csi0 to csi2 parameter symbol conditions min. max. unit sckn cycle <67> t cysk1 output 120 ns sckn high-level width <68> t wskh1 output 0.5t cysk1 20 ns sckn low-level width <69> t wskl1 output 0.5t cysk1 20 ns sin setup time (to sckn ) <70> t ssisk1 30 ns sin hold time (from sckn ) <71> t hsksi1 0 ns son output delay time (from sckn ) <72> t dskso1 18 ns son output hold time (from sckn ) <73> t hskso1 0.5t cysk1 5ns remark n = 0 to 2 (ii) timing of csi3 parameter symbol conditions min. max. unit sck3 cycle <67> t cysk3 output r l = 1.5 k ? 500 ns sck3 high-level width <68> t wskh3 output c l = 50 pf 0.5t cysk3 70 ns sck3 low-level width <69> t wskl3 output 0.5t cysk3 70 ns si3 setup time (to sck3 ) <70> t ssisk3 100 ns si3 hold time (from sck3 ) <71> t hsksi3 50 ns so3 output delay time (from sck3 ) <72> t dskso3 r l = 1.5 k ? 150 ns so3 output hold time (from sck3 ) <73> t hskso3 c l = 50 pf 0.5t cysk3 5ns remark r l and c l are the load resistance and load capacitance of the sck3 and so3 output lines. (b) slave mode (i) timing of csi0 to csi2 parameter symbol conditions min. max. unit sckn cycle <67> t cysk2 input 120 ns sckn high-level width <68> t wskh2 input 30 ns sckn low-level width <69> t wskl2 input 30 ns sin setup time (to sckn ) <70> t ssisk2 10 ns sin hold time (from sckn ) <71> t hsksi2 10 ns son output delay time (from sckn ) <72> t dskso2 30 ns son output hold time (from sckn ) <73> t hskso2 t wskh2 ns remark n = 0 to 2
31 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds (9) csi timing (2/2) (ii) timing of csi3 parameter symbol conditions min. max. unit sck3 cycle <67> t cysk4 input 500 ns sck3 high-level width <68> t wskh4 input 180 ns sck3 low-level width <69> t wskl4 input 180 ns si3 setup time (to sck3 ) <70> t ssisk4 100 ns si3 hold time (from sck3 ) <71> t hsksi4 50 ns so3 output delay time (from sck3 ) <72> t dskso4 r l = 1.5 k ? 150 ns so3 output hold time (from sck3 ) <73> t hskso4 c l = 50 pf t wskh4 ns remark r l and c l are the load resistance and load capacitance of the sck3 and so3 output lines. sckn (i/o) sin (input) son (output) <67> <69> <68> <70> <71> <72> <73> input data output data remarks 1. broken lines indicate high impedance. 2. n = 0 to 3
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 32 data sheet u13188ej6v0ds (10) rpu timing parameter symbol conditions min. max. unit ti1n high-level width <74> t wtih 3t + 10 ns ti1n low-level width <75> t wtil 3t + 10 ns tclr1n high-level width <76> t wtch 3t + 10 ns tclr1n low-level width <77> t wtcl 3t + 10 ns remark t = t cyk remark n = 1 to 4 ti1n (input) <74> <75> tclr1n (input) <76> <77>
33 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds a/d converter characteristics (t a = 40 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 4.5 v av ref1 av dd 0.4 %fsr 3.5 v av ref1 av dd 0.7 %fsr quantization error 1/2 lsb conversion time t conv 4.5 v av ref1 av dd 60 t cyk 3.5 v av ref1 av dd 60 t cyk sampling time t samp 4.5 v av ref1 av dd 10 t cyk 3.5 v av ref1 av dd 10 t cyk zero-scale error note 1 4.5 v av ref1 av dd 1.5 3.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb full-scale error note 1 4.5 v av ref1 av dd 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb non-linearity error note 1 4.5 v av ref1 av dd 1.5 2.5 lsb 3.5 v av ref1 av dd 1.5 4.5 lsb analog input v ian 0.3 av dd + 0.3 v voltage note 2 reference voltage av ref1 3.5 av dd v av ref1 current ai ref1 1.2 3.0 ma av dd supply current ai dd 2.3 6.0 ma notes 1. excludes quantization error. 2. when v ian = 0, the conversion result becomes 000h. when 0 < v ian < av ref1 , conversion has 10-bit resolution. when av ref1 v ian av dd , the conversion result becomes 3ffh.
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 34 data sheet u13188ej6v0ds parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error load condition: 2 m ? , 30 pf 0.8 % av ref2 = v dd av ref3 = 0 load condition: 2 m ? , 30 pf 1.0 % av ref2 = 0.75v dd av ref3 = 0.25v dd load condition: 4 m ? , 30 pf 0.6 % av ref2 = v dd av ref3 = 0 load condition: 4 m ? , 30 pf 0.8 % av ref2 = 0.75v dd av ref3 = 0.25v dd settling time load condition: 2 m ? , 30 pf 10 s output resistance ro 8 k ? av ref2 input voltage av ref2 0.75v dd v dd v av ref3 input voltage av ref3 0 0.25v dd v resistance between r airef dacs0, dacs1 = 55h 2 4 k ? av ref2 and av ref3 d/a converter characteristics (t a = 40 to +85 c, v dd = av dd = 5 v 10%, v ss = av ss = 0 v)
35 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds 4. package drawing 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 36 data sheet u13188ej6v0ds 5. recommended soldering conditions the pd703003a, 703004a, 703025a, 703003a(a), and 703025a(a) should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representatives. table 5-1. soldering conditions pd703003agc-33- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703004agc-33- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703025agc-33- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703003agc(a)-33- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703025agc(a)-33- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow ir35-107-2 vps vp15-107-2 partial heating note after opening a dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) package peak temperature: 215 c, time: 25 to 40 seconds (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) pin temperature: 300 c max., time 3 seconds max. (per pin row)
37 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds appendix notes on target system design the following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. target system note yqsocket100sdn (included with ie-703002-mc) can be inserted here to adjust the height (height: 3.2 mm). nqpack100sd yqpack100sd 132.24 mm note in-circuit emulator option board conversion connector ie-703003-mc-em1 side view top view connection condition diagram in-circuit emulator ie-703002-mc yqguide target system yqpack100sd, nqpack100sd, yqguide ie-703003-mc-em1 ie-703002-mc pin 1 position 13.3 mm 24 mm 21.58 mm 15.24 mm 75 mm 31.84 mm target system nqpack100sd yqpack100sd ie-703003-mc-em1 connect to ie-703002-mc. yqguide pin 1 position
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) 38 data sheet u13188ej6v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. related documents pd70f3003a, 70f3025a, 70f3003a(a) data sheet (u13189e) the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850 series and v853 are trademarks of nec corporation.
39 pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) data sheet u13188ej6v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v?lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
pd703003a, 703004a, 703025a, 703003a(a), 703025a(a) the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of november, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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